The Night-Before Playbook

Step 1 — pFET: Gate = 0 V, source at V_DD = 3.3 V (higher side for pFET). V_SG = 3.3−0 = 3.3 V > |V_Tp| = 0.7 V ⇒ ON. Passes logic-1: V_x from pFET = V_DD = 3.3 V (strong 1, pFET passes 1 cleanly).

Step 2 — nFET: Gate = V_DD = 3.3 V. It connects V_x to 0 V. nFET passes 0 V upward — strong 0. So it tries to pull V_x to 0 V.

Conflict: Both ON simultaneously ⇒ V_x is a contested (ratioed) node — its steady-state depends on the relative drive strengths (W/L ratios) of the two transistors. This is a static power dissipation / crowbar current situation, which is not a valid CMOS design. In a well-designed circuit, only one should be ON at a time.

The key faculty step: always identify which terminal is source (higher-voltage side for pFET, lower-voltage side for nFET) before applying the pass rules.

Clamp ceiling = V_G−V_Tn = 1.8−0.4 = 1.4 V.

V_out = Min[1.5, 1.4] = 1.4 V (clamped — weak 1).

V_out = Max[(V_G+|V_Tp|), V_in] = Max[(0+0.6), 0.3] = Max[0.6, 0.3] = 0.6 V (clamped at |V_Tp| — weak 0, cannot pass a clean 0).

M₁ ceiling = 5−0.7 = 4.3 V. V_out1 = Min[5, 4.3] = 4.3 V.

M₂ ceiling = 5−0.7 = 4.3 V. V_out2 = Min[4.3, 4.3] = 4.3 V (no further drop).

M₃ ceiling = 5−0.7 = 4.3 V. V_out3 = Min[4.3, 4.3] = 4.3 V.

Answer: 4.3 V. Same result as Example 2 — in a series chain (all gates at V_DD), only the first transistor clips the voltage. Subsequent ones pass it through unchanged.

Ceiling = V_G−V_Tn = 2.5−0.5 = 2.0 V.

• V_in = 0 V: Min[0, 2.0] = 0 V (strong 0, passes cleanly).
• V_in = 1.8 V: Min[1.8, 2.0] = 1.8 V (unclamped, below ceiling).
• V_in = 3.3 V: Min[3.3, 2.0] = 2.0 V (clamped — weak 1).

When an nFET tries to pass V_DD, its source rises toward V_DD. Since the gate is at V_DD, V_GS = V_G−V_S keeps shrinking. Once V_S reaches V_DD−V_Tn, we have V_GS = V_Tn and the transistor is at the edge of cutoff — it can no longer sustain drain current. The output is therefore stuck at V_DD−V_Tn (a “weak 1”).

A pFET with gate at 0 V passing V_DD has V_SG = V_DD−0 = V_DD, which stays well above |V_Tp| — it remains fully ON and drives the output all the way to V_DD (strong 1, no threshold loss).

NAND2: f = (AB)', f' = AB. Literals in f' = 2 → 2N + 2P = 4T.
PDN: A series B (AND → series nFETs) to GND.
PUN (dual): A parallel B (series → parallel pFETs) to V_DD.

NOR2: f = (A+B)', f' = A+B. Literals in f' = 2 → 2N + 2P = 4T.
PDN: A parallel B (OR → parallel nFETs) to GND.
PUN (dual): A series B (parallel → series pFETs) to V_DD.

Both use 4 transistors. Difference is topology: NAND has series PDN/parallel PUN; NOR has parallel PDN/series PUN. Series PMOS in NOR is slower to pull up (pFET mobility is lower), so NAND is generally preferred.

Step 1 — Dual the PUN to get the PDN:
PUN: A series (B ∥ C) → PDN: A parallel (B series C).
So PDN = nFET A in parallel with (nFET B in series with nFET C), all between output and GND.

Step 2 — Read f' from PDN:
PDN expression: f' = A + BC (parallel = OR, series = AND).

Step 3 — Find f:
f = (A + BC)' = A'·(BC)' = A'·(B' + C') (DeMorgan).

Verification from PUN: PUN conducts when A=0 AND (B=0 OR C=0), i.e., A'·(B'+C') ✓.

Step 1 — Simplify:
f = (A+B+C)' + A'B = A'B'C' + A'B = A'(B'C' + B) = A'(B + B'C') = A'(B + C')  [absorption: B + B'C' = B + C'].

Step 2 — Express as MUX-style TG decomposition on variable A:
When A=0: f = B + C'.
When A=1: f = 0.

So: f = (B + C')·A' + 0·A = (B + C')·A'.

Step 3 — Build:

• TG₀ controlled by A'/A: passes input (B + C') when A=0.
• TG₁ controlled by A/A': passes 0 (GND) when A=1.
• Need (B + C') = NOR(B',C) inverted… simplest: build (B+C') with a NOR gate on B' and C, but since we need complement inputs anyway, use a CMOS NOR/OR or another TG level.

Most efficient: generate (B + C') via TG decomposition on B:
When B=1: (B+C') = 1 → output = V_DD.
When B=0: (B+C') = C'.

So (B+C') = 1·B + C'·B' → TG pair: one passes V_DD when B=1, one passes C' when B=0.

Final circuit:
• 1 inverter for A → A' (2T).
• 1 inverter for C → C' (2T).
• TG pair for (B+C'): TG passes V_DD when B=1, TG passes C' when B=0 (4T).
• TG pair for final MUX on A: TG passes (B+C') when A=0, TG passes GND when A=1 (4T — but TG passing constant GND can be a single nFET tied to GND, saving 1T, so 3T or keep 4T for clean design).
Total: 12T (vs. 16T for a direct CMOS implementation of the unsimplified expression).

Step 1: f = (AB + C)', so f' = AB + C.

Step 2: Literals in f' = 3 (A, B, C) → 3 NMOS + 3 PMOS = 6 transistors.

Step 3 — PDN (from f' = AB + C):
OR of two terms → two parallel branches to GND.
Branch 1: A series B (AND).
Branch 2: C alone.
So: (nFET A ser nFET B) ∥ (nFET C), all between output and GND.

Step 4 — PUN (dual):
Parallel → series, series → parallel.
The outer parallel becomes series: two groups in series from V_DD to output.
Group 1 (dual of A ser B): pFET A ∥ pFET B.
Group 2 (dual of C alone): pFET C.
So: (pFET A ∥ pFET B) in series with pFET C, from V_DD to output.

Answer: 6T AOI gate. Output = (AB + C)'.

Step 1: f = (A + BC)', so f' = A + BC.

Step 2: Literals in f' = 3 → 3 NMOS + 3 PMOS = 6 transistors.

Step 3 — PDN (from f' = A + BC):
OR → parallel branches.
Branch 1: nFET A alone.
Branch 2: nFET B in series with nFET C (AND).
Result: nFET A ∥ (nFET B ser nFET C) between output and GND.

Step 4 — PUN (dual):
Outer parallel → series. Inner series → parallel.
Group 1: pFET A alone.
Group 2: pFET B ∥ pFET C.
Result: pFET A in series with (pFET B ∥ pFET C), from V_DD to output.

Answer: 6T OAI gate. Output = (A + BC)'.

TG decomposition on variable A:
When A=0: f = 0⊕B = B.
When A=1: f = 1⊕B = B'.

So: f = B·A' + B'·A (this is the canonical XOR form, and it maps directly to a 2:1 TG MUX).

Circuit:
• TG₀ controlled by A'/A: passes B when A=0.
• TG₁ controlled by A/A': passes B' when A=1.
• Need A' (1 inverter = 2T) and B' (1 inverter = 2T).
• 2 TGs = 4T.

Total: 8 transistors (2 TGs + 2 inverters). This matches the faculty's 8T XOR count from the notes.

1. Effective squares: n_eff = 8 + 0.635 × 3 = 8 + 1.905 = 9.905
2. R_line = 25 × 9.905 = 247.6 Ω
3. Total geometric squares = 8 + 3 = 11 → l = 11 × 3 µm = 33 µm
4. C_line = (3.9 × 8.854 × 10⁻¹²) × (3 × 10⁻⁶) × (33 × 10⁻⁶) / (800 × 10⁻¹⁰)
   = 34.531 × 10⁻¹² × 99 × 10⁻¹² / 8 × 10⁻⁸
   = 3418.6 × 10⁻²⁴ / 8 × 10⁻⁸ = 42.73 fF
5. τ = 247.6 × 42.73 × 10⁻¹⁵ = 10.58 ps

• (a) n-well — Visible Feature (physical structure in the substrate)
• (b) Active mask — Mask Layer (defines where field oxide is absent; "active = NOT FOX")
• (c) p+ source/drain — Visible Feature (physical doped region)
• (d) Poly patterning mask — Mask Layer (defines polysilicon gate geometry)
• (e) Gate oxide — Visible Feature (physical; self-aligned to poly — no separate oxide mask exists)
• (f) n+ doping mask — Mask Layer (defines where n-type implant is applied)

NMOS pull-down (conducts when A(B+C) = 1): A in series with (B ∥ C).

• Nodes: Out, N1, GND
• Edges: A (Out—N1), B (N1—GND), C (N1—GND)

PMOS pull-up (conducts when complement = A′ + B′C′): A in parallel with (B series C).

• Nodes: V_DD, N2, Out
• Edges: A (V_DD—Out), B (V_DD—N2), C (N2—Out)

NMOS path: Out →^A N1 →^B GND →^C N1 → edge order: A, B, C

PMOS path: Out →^A V_DD →^B N2 →^C Out → edge order: A, B, C

Common Euler path ∴ poly order: A, B, C.

The gate oxide is grown everywhere over the active area, and the polysilicon gate is patterned on top of it. The poly gate itself defines where the channel forms beneath — the oxide under the poly becomes the gate oxide, while oxide elsewhere is irrelevant (or etched away for contacts). Because the gate region is defined by the poly mask, not by a separate oxide mask, we say the gate oxide is self-aligned to the poly gate. This eliminates an entire mask step and avoids alignment errors between the gate and the channel.

Errors:

• Metal1 is above poly, not below it. Poly is deposited on the gate oxide; Metal1 comes after the first inter-level oxide (Ox1).
• Contacts connect poly/active to Metal1 — they sit between active/poly and Metal1, not above Metal2.

Correct order (bottom → top): Active → Poly gate → Ox1 (with contact holes) → Contacts → Metal1 → Ox2 → Via → Metal2.

• Trace A: n_eff = 20; R_A = 30 × 20 = 600 Ω
• Trace B: n_eff = 14 + 0.635 × 6 = 14 + 3.81 = 17.81; R_B = 30 × 17.81 = 534.3 Ω

Trace B has lower resistance by 600 − 534.3 = 65.7 Ω (≈ 11% less), despite the same geometric footprint area. Corners spread current across a wider cross-section, reducing effective resistance per square. Note: both traces have the same capacitance (same geometric area), so Trace B also has a lower τ.

Given: t_ox = 120 Å, N_a = 8 × 10¹⁴ cm⁻³, V_T0n = 0.55 V, W/L = 10, μ_n = 540 cm²/V·s.

1. C_ox: C_ox = 3.9 × 8.854 × 10⁻¹⁴ / (120 × 10⁻⁸) = 3.453 × 10⁻⁷ / 1.2 × 10⁻⁵ = 2.878 × 10⁻⁷ F/cm².
2. γ: γ = √(2 × 1.6 × 10⁻¹⁹ × 11.8 × 8.854 × 10⁻¹⁴ × 8 × 10¹⁴) / C_ox = 0.0568 V^0.5.
3. 2|φ_F|: |φ_F| = (kT/q) · ln(N_a/n_i) = 0.026 × ln(8 × 10¹⁴ / 1.45 × 10¹⁰) = 0.026 × ln(5.517 × 10⁴) = 0.026 × 10.92 = 0.284 V. So 2|φ_F| = 0.568 V.
4. (a) V_SBn = 2 V: V_Tn = 0.55 + 0.0568 × (√(0.568 + 2) − √0.568) = 0.55 + 0.0568 × (√2.568 − √0.568) = 0.55 + 0.0568 × (1.603 − 0.754) = 0.55 + 0.0568 × 0.849 = 0.55 + 0.048 = 0.598 V.
5. (b) V_SBn = 3 V: V_Tn = 0.55 + 0.0568 × (√3.568 − √0.568) = 0.55 + 0.0568 × (1.889 − 0.754) = 0.55 + 0.0568 × 1.135 = 0.55 + 0.064 = 0.614 V.
6. At V_GSn = 3 V, V_DSn = 3 V, V_Tn = 0.614 V: V_DS,sat = 3 − 0.614 = 2.386 V < V_DSn = 3 V → Saturation. I_Dn = (μ_n · C_ox / 2) · (W/L) · (V_GSn − V_Tn)² = (540 × 2.878 × 10⁻⁷ / 2) × 10 × (2.386)² ≈ 442.31 μA.

Check: V_GSn = 0.5 V < V_Tn = 0.8 V → Cutoff region.

I_Dn = 0. The channel has not formed; no conduction regardless of V_DSn.

1. V_DS,sat = V_GSn − V_Tn = 2.5 − 0.6 = 1.9 V.
2. V_DSn = 0.5 V < V_DS,sat = 1.9 V → Triode region.
3. I_Dn = k′_n(W/L)[(V_GSn − V_Tn)V_DSn − V_DSn²/2] = 150 × 10⁻⁶ × 8 × [(1.9)(0.5) − (0.5)²/2] = 1200 × 10⁻⁶ × [0.95 − 0.125] = 1200 × 10⁻⁶ × 0.825 = 990 μA = 0.99 mA.

1. V_DS,sat = V_GSn − V_Tn = 1.8 − 0.5 = 1.3 V.
2. V_DSn = 3 V > V_DS,sat = 1.3 V → Saturation region.
3. I_Dn = (1/2) · k′_n · (W/L) · (V_GSn − V_Tn)² = (200 × 10⁻⁶ / 2) × 12 × (1.3)² = 100 × 10⁻⁶ × 12 × 1.69 = 2028 μA = 2.028 mA.

1. V_SD,sat = V_SGp − |V_Tp| = 2.2 − 0.7 = 1.5 V.
2. V_SDp = 0.8 V < V_SD,sat = 1.5 V → Triode region.
3. I_Dp = (β_p/2) · [2(V_SGp − |V_Tp|)V_SDp − V_SDp²] = (80 × 10⁻⁶ × 15 / 2) × [2 × 1.5 × 0.8 − (0.8)²] = 600 × 10⁻⁶ × [2.4 − 0.64] = 600 × 10⁻⁶ × 1.76 = 1056 μA = 1.056 mA.

Once V_DSn ≥ V_DS,sat = V_GSn − V_Tn, the channel is pinched off at the drain end — the inversion charge Q_e(y = L) drops to zero. Any further increase in V_DSn simply widens the depletion region beyond the pinch-off point; the voltage across the inverted portion of the channel stays fixed at V_DS,sat. Since the current through the channel depends only on the charge profile from source to pinch-off, and that profile is set entirely by V_GSn − V_Tn, the current I_Dn = (β_n/2)(V_GSn − V_Tn)² has no V_DSn term — it is constant. The λ correction adds back a weak V_DSn dependence via the effective channel-length shortening (ΔL increases with V_DSn).

Dimensions: L' = 2/2 = 1 μm, W' = 4/2 = 2 μm, t_ox' = 400/2 = 200 Å.

Voltages (÷S): V_DD' = 5/2 = 2.5 V, V_T0' = 1/2 = 0.5 V.

Doping (×S): N'_A = 2 · N_A.

C_ox (×S): C_ox' = 2 · C_ox.

Current (÷S): I_D' = 2/2 = 1 mA.

Power (÷S²): P_D = 5 × 2 = 10 mW → P_D' = 10/4 = 2.5 mW. Check: 2.5 × 1 = 2.5 mW ✓.

Area: Before = 2 × 4 = 8 μm². After = 1 × 2 = 2 μm².

Power density: Before = 10/8 = 1.25 mW/μm². After = 2.5/2 = 1.25 mW/μm². Unchanged ✓.

Dimensions (÷S): L' = 1.5/1.5 = 1 μm, W' = 3/1.5 = 2 μm, t_ox' = 300/1.5 = 200 Å.

Voltages: V_DD' = 5 V, V_T0' = 0.8 V (both unchanged).

Doping (×S²): N'_A = 1.5² · N_A = 2.25 · N_A.

C_ox (×S): C_ox' = 1.5 · C_ox.

Current (×S): I_D' = 1.5 × 0.5 = 0.75 mA.

Power (×S): P_D = 5 × 0.5 = 2.5 mW → P_D' = 5 × 0.75 = 3.75 mW.

Area: Before = 1.5 × 3 = 4.5 μm². After = 1 × 2 = 2 μm².

Power density: Before = 2.5/4.5 ≈ 0.556 mW/μm². After = 3.75/2 = 1.875 mW/μm².

Ratio = 1.875 / 0.556 = 3.375 = S³ = 1.5³ ✓. Power density increases by a factor of 3.375.

Constant-voltage scaling is not sustainable. Although dimensions shrink, voltages remain fixed, so the electric field inside the device increases by S each generation. This causes power density to blow up by S³ per generation — even a modest S = 1.5 gives a 3.375× increase per step. After just a few generations the chip becomes impossible to cool. The industry therefore adopted constant-field (full) scaling, which scales voltages down alongside dimensions, keeping both the electric field and the power density unchanged.

Under full scaling, V_T0 is divided by S — it scales down in proportion with all other voltages (V_DD, V_T0). This ensures that the overdrive voltage (V_GSn − V_Tn) also scales by 1/S, preserving the same electric-field conditions inside the device. Under constant-voltage scaling, V_T0 is unchanged.

No. Both W and L are divided by the same factor S in both scaling approaches. Therefore W'/L' = (W/S)/(L/S) = W/L. The aspect ratio — and hence the device transconductance parameter β = k'·(W/L) up to the k' factor — is geometrically preserved. (β itself does change because k' = μ·C_ox scales up by S via the thinner oxide.)

It stays the same. R_n = 1/[β_n·(V_DD − V_Tn)]. Under full scaling β' = S·β (because C_ox scales up by S while W/L is unchanged), and (V_DD−V_Tn) scales down by S. The S factors cancel: R' = 1/[S·β · (V_DD−V_Tn)/S] = 1/[β·(V_DD−V_Tn)] = R. This is a common exam trip-up — resistance does not shrink with geometry under full scaling because the voltage headroom shrinks in exact proportion to the transconductance increase.

Apply: T_D = R₁C₁ + (R₁+R₂)C₂ + (R₁+R₂+R₃)C₃

Term 1: 200 × 50 × 10⁻¹⁵ = 10.0 ps

Term 2: (200 + 300) × 80 × 10⁻¹⁵ = 500 × 80 × 10⁻¹⁵ = 40.0 ps

Term 3: (200 + 300 + 150) × 60 × 10⁻¹⁵ = 650 × 60 × 10⁻¹⁵ = 39.0 ps

T_D = 10.0 + 40.0 + 39.0 = 89.0 ps

β_n = k'_n · (W/L) = 120 × 10⁻⁶ × (8/0.5) = 120 × 10⁻⁶ × 16 = 1.92 × 10⁻³ A/V²

R_n = 1 / [β_n · (V_DD − V_Tn)] = 1 / [1.92 × 10⁻³ × 2.65] = 1 / (5.088 × 10⁻³)

R_n ≈ 196.5 Ω

C_G = C_ox · W · L' = 3.45 × 10 × 0.35 = 12.075 fF

C_GS = C_GD = 0.5 × 12.075 = 6.0375 fF

The MOSFET's actual I-V characteristic is highly non-linear (quadratic in saturation, roughly linear in deep triode). Exact delay analysis would require solving an ODE with a voltage-dependent current source at every instant. By replacing the transistor with a fixed linear resistance R_n (or R_p), the RC network becomes a simple linear circuit whose delay is analytically tractable via Elmore or first-order RC time-constant analysis. The η parameter absorbs the averaged effect of the transistor operating across multiple regions during a single switching transition, giving a single effective R that reproduces the approximate 50%-point delay.

η is a fitting coefficient (ranging 1–6) that accounts for the fact that during a switching event the MOSFET sweeps through cutoff, saturation, and triode regions — its instantaneous resistance is not constant. Different values of η correspond to different weighting of these regions on the average resistance. Setting η = 1 corresponds to the simplest approximation: using the deep-triode (small V_DS) resistance as the single equivalent value. The faculty uses η = 1 because it gives compact, closed-form answers suitable for quick exam calculations and matches the worked numericals in the course material.

From R_n = 1 / [k'_n · (W/L) · (V_DD − V_Tn)]:

W/L ≥ 1 / [R_n · k'_n · (V_DD − V_Tn)]

= 1 / [500 × 110 × 10⁻⁶ × 4.3]

= 1 / [500 × 4.73 × 10⁻⁴]

= 1 / 0.2365

W/L ≥ 4.23

(For L = 0.5 μm this means W ≥ 2.11 μm.)